In this presentation, we’ll take a look at the bottom of the verification and monitoring stack. Firstly, we give an overview over hardware-level event sources, such as processor tracing facilities, and how to integrate them into monitoring approaches. Secondly, we discuss approaches to processing events in hardware on FPGAs of SoC or accelerator cards. We conclude with an in-depth look at a fully integrated hardware-assisted approach to detection of data races based on i) hardware traces, ii) hardware monitoring, and iii) the high-level specification language TeSSLa that has been used to synthesize reconfigurable monitors for deployment onto FPGAs.
Mon 6 JunDisplayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change
13:30 - 15:00
|Hardware-assisted Runtime Monitoring
I: Volker Stolz Høgskulen på VestlandetLink to publication
|Predictive Semantics for Past-CTL Runtime Monitors
|HIBOU : Tooling Offline Runtime Verification against Interaction Models